1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a compensation element.
Priority is claimed on Japanese Patent Application No. 2010-093557, Apr. 14, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Semiconductor devices are used in various fields, such as personal computers, communication equipment, home appliances, toys, and the like.
The semiconductor devices operate as key devices in a system used. The semiconductor device has been improved in large scale and high speed performance, causing a power supply line to increase its noise. The development period of the semiconductor device can be shortened by design automation and block solution is applied. The block solution includes the following steps. Circuit cells having a fixed height and constituting various logic circuits are arranged. The arranged circuit cells are connected to each other based on circuit connection information. A circuit design and a mask layout design are almost entirely automated and performed as a CAD by the block solution. However, a semiautomatic design of a compensation element such as a compensation capacitor for reducing noise of the power supply is performed.
For example, the variation of power supply voltage is suppressed by arranging a compensation capacitor between power supply lines so as to reduce noise of the power supply lines. Compensation elements such as compensation capacitors of the power supply voltages are not directly related to a logic operation. However, the compensation elements are indispensable elements for preventing erroneous operations and maintaining high reliability. Despite this, after transistors are designed on the basis of circuit information, the compensation elements are arranged and laid out under the power supply lines or around a chip, according to experiences of an engineer.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-253393 discloses that transistors as functional elements are arranged adjacent to a boundary between a P-channel region and an N-channel region (hereinafter, referred to as a “PN boundary”) of a circuit cell as shown in FIGS. 1 and 3 to 5. The P-channel region is a semiconductor region in which P-channel transistors are formed. The P-channel region is another semiconductor region in which P-channel transistors are formed. The P-channel region and N-channel region are bounded. The semiconductor region in which P-channel transistors are formed will hereinafter be referred to as “P-channel region”. The semiconductor region in which N-channel transistors are formed will hereinafter be referred to as “N-channel region”. Compensation capacitors are formed in spaces, in which the functional elements are not arranged, in each of the P-channel region and the N-channel region.
The functional element (transistor) is an element necessary to perform a predetermined operation of its circuit cell. More specifically, a P-type transistor is arranged as the functional element adjacent to the PN boundary in the P-channel region, and an N-type transistor is arranged as the functional element adjacent to the PN boundary in the N-channel region.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-253393 suggests, but does not disclose, that a plurality of signal lines SL are arranged to transmit a signal between circuit cells over a plurality of circuit cells. The plurality of circuit cells are arranged along an extension direction (x-direction) of power supply lines VDD and VSS. The plurality of signal lines are arranged to extend in the x-direction. In order to supply signals to predetermined circuit cells, the plurality of signal lines are connected to gate wirings through contact holes. The gate wiring connects gate electrodes of the P-type transistor and the N-type transistor which are formed in the P-type channel region and the N-type channel region, respectively. The gate wiring prevents insulation breakdown at a gate insulating film or an insulating film formed on a sidewall of the gate electrode in fabrication. When the contact hole is directly on a gate electrode, such insulation breakdown may be caused.